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Go to next pageMidas Consulting - Richardson, Texas, United States, 75080
Customer : On Semi
Senior Memory IP Designer
Location : Bay Area, CA and Richardson, TX (On-site)
Fulltime/Contract both
Rate- $55-60/hr on C2C (DOE)
Desired Skillsets:
Responsibility for Architecting and Developing custom Memory IP as key member of the Central IP organization• rchitect, design and build memories and memory sub-systems at the gate and transistor level• Create test benches, simulate, and analyze the results of your designs• Perform parasitic extraction and post-layout simulations and analyze results• Work closely with the organization's layout team to optimize area and performance of memory leaf cell designs you create• Floorplan the physical design and leaf cell layout integration required to complete the macro• Create design specifications and datasheets used by consumers of the memory IP• Work closely with the IP Automation team who will turn your designs into memory compilers used by our internal customers• Work directly with the validation and qualification teams to help specify test chips and test plans for all post silicon activities
Qualifications
Technical Qualifications & Skills• Minimum BS/MS in Electrical Engineering or related technical field• 8-10 plus years SRAM and ROM design experience• Solid understanding of semiconductor device physics• Demonstrable experience with liberty timing views and Verilog RTL• Expert level understanding of variation analysis and design margining required to produce high yielding circuits• Proficiency in running simulations, scripting and is up to date on most commonly used design tools• Good, working level understanding of EM/IR Analysis, DFT and DFM methodologies• Solid communication, presentation and interpersonal skills• Design experience with floating gate NVM and OTP design a plus
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Senior Memory IP Designer